In order to provide for shallower source/drain and gate electrodes with minimal sheet resistance, it has been proposed to employ self-aligned tungsten strapped source/drain and gate. For example, Sekine, et al. in Self-aligned Tungsten Strapped Source/Drain and Gate Technology, Realizing the Lowest Sheet Resistance for Subquarter Micro CMOS IEDM 94, pp 493-496 have set forth a method for forming such tungsten strapped source/drain and gate. This methodology used selective etching of phosphorus doped silicon glass followed by selective tungsten chemical vapor deposition to provide such self-aligned tungsten strapped source/drain and gate.
The problem with this technology is that it does not permit formation of polysilicon resistors on the same polysilicon layer as the gate electrode. The tungsten cladding over the gate polysilicon interferes with this process. Further, phosphorus in the phosphorus doped silicon glass can migrate into the silicon, altering its resistance. Therefore, in order to provide polysilicon resistors, a second polysilicon layer had to be employed with isolation layers and contacts.